The present invention relates to a bit line over-driving scheme in a semiconductor memory device, and more particularly, an over-driving pulse generating circuit for controlling an over-driver.
As a continuous scale-down with respect to a line width and size of cells constituting a semiconductor memory chip has progressed, a voltage lowering of a power supply voltage has accelerated, and accordingly, there has been a demand for a design technique for satisfying a performance required under low power voltage condition.
Now, most semiconductor memory chips are equipped with an internal voltage generator for generating an inner voltage to supply itself with a voltage required for operating an internal circuit in a chip. In a case of a memory device, inter alia, employing a bit line sensing amplifier, such as a dynamic random access memory (DRAM), a core voltage VCORE is used for sensing a cell data.
When a word line selected by a row address is activated, data from a plurality of memory cells connected to the word line is transmitted to a bit line and the bit line sensing amplifier senses and amplifies a voltage difference between bit line pair. Typically, there are thousands of bit line sensing amplifiers, which may be simultaneously operated, in a semiconductor memory chip. In such a case, much current is consumed in a core voltage stage used to drive a pull-up supply line (usually, referred to as RTO) of the bit line sensing amplifiers. It is, however, difficult to amplify data in a great deal of cells by using the core voltage VCORE for short time in a trend in lowering an operational voltage.
In order to solve the above problem, in an initial operation of the bit line sensing amplifier, i.e., directly after sharing charges between the memory cells and the bit line, an over-driving scheme for the bit line sensing amplifier is employed to drive the RTO of the bit line sensing amplifier in a higher voltage (usually, a power supply voltage VDD) than the core voltage VCORE for a constant time period.
FIG. 1 shows a block diagram for illustrating a configuration of a bit line sensing amplifier array employing an over-driving scheme.
As shown, the bit line sensing amplifier array includes a bit line sensing amplifier 30, an upper bit line separating unit 10, a lower bit line separating unit 50, a bit line equalizing/pre-charging unit 20, a column selecting unit 40, and a bit line sensing amplifier (BLSA) supply line driving unit 60, without respect of employing the over-driving scheme.
The upper bit line separating unit 10 decouples and couples an upper memory cell array and the bit line sensing amplifier 30 in response to an upper separate signal BISH, and the lower bit line separating unit 50 decouples and couples a lower memory cell array and the bit line sensing amplifier 30 in response to a lower separate signal BISL.
The bit line sensing amplifier 30 senses a voltage difference between a bit line pair BL and BLB, the bit line pair having a fine voltage difference in a charge sharing state, when an enable signal is activated to drive a pull-down supply line (usually, referred to as a SB) and a pull-up supply line (usually, referred to as a RTO) to a predetermined voltage level. Further, it amplifies one of the supply lines to have a ground voltage VSS and the other of them to have a core voltage VCORE.
The bit line equalizing/pre-charging unit 20 pre-charges the bit line pair BL and BLB to a bit line pre-charge voltage VBLP, usually a half of the core voltage VCORE (VCORE/2), in response a bit line equalizing signal BLEQ, after completing sensing, amplifying and restoring processes with respect to the bit lines.
The column selecting unit 40 transmits data sensed and amplified by the bit line sensing amplifier 30 to segment data buses SIO and SIOB, in response to a column selective signal YI, when a read command is applied thereto.
The BLSA supply line driving unit 60 has a P-type metal-oxide semiconductor (PMOS) transistor M2 for driving the RTO to the core voltage VCORE in response to a pull-up supply line driving control signal SAP, an N-type metal-oxide semiconductor (NMOS) transistor M3 for driving the SB to the ground voltage VSS in response to a pull-down supply line driving control signal SAN, a PMOS transistor M1 as an over-driver for driving the core voltage VCORE to the power supply voltage VDD in response to an over-driving pulse SAOVDP (i.e., an over-driver control signal), and a BLSA supply line equalizing/pre-charging section 62 for pre-charging the RTO and SB of the bit line sensing amplifier 30 to a bit line pre-charge voltage VBLP in response to the bit line equalizing signal BLEQ.
While, for the convenience of the explanation, the over-driving pulse SAOVDP is defined as a low active pulse and the over-driver enabled by the over-driving pulse SAOVDP is implemented by the PMOS transistor M1, an NMOS transistor may be used as the over-driver instead of the PMOS transistor M1. Similarly, an NMOS transistor may be replaced with the PMOS transistor M2 controlled by the pull-up supply line driving control signal SAP.
FIG. 2 shows a block diagram of an over-driving pulse output unit for generating the over-driving pulse SAOVDP.
As shown, the over-driving pulse output unit includes an enable signal generator 200, supply line driving control signal generator 210, and an over-driving pulse generator 220.
The enable signal generator 200 generates a BLSA enable signal SAEN in response to an active command ACT and a pre-charge command PCG. The supply line driving control signal generator 210 generates a pull-up supply line driving control signal SAP, a pull-down supply line driving control signal SAN and an over-driving signal OVD by using the BLSA enable signal SAEN. The over-driving pulse generator 220 for receiving the over-driving signal OVD to generate the over-driving pulse SAOVDP.
FIG. 3 shows a circuit diagram for illustrating a configuration of the over-driving pulse generator 220 shown in FIG. 2.
The over-driving pulse generator 220 includes a delay section and a NOR gate NOR10. The delay section delays the over-driving signal OVD by a predetermined time period. The NOR gate NOR10 performs a NOR operation on a delayed over-driving signal output from the delay section and the over-driving signal OVD to output the over-driving pulse SAOVDP.
FIG. 4 is a waveform diagram illustrating signals output from the over-driving pulse generator 220 shown in FIG. 3.
Hereinafter, an operation of the BLSA supply line driving unit 60 is described.
The active command ACT is applied to activate a word line and data stored in a cell is deserted into a bit line pair BL and BLB by a charge sharing. After a predetermined time period, the pull-up supply line driving control signal SAP is activated with a logic low level and the pull-down supply line driving control signal SAN is activated with a logic high level. In this case, the RTO is over-driven by the over-driving pulse SAOVDP activated with a logic low level by receiving the active command ACT before (at least simultaneously with) the pull-up and pull-down supply line driving control signals SAP and SAN. That is, when all of the pull-up and pull-down supply line driving control signals SAP and SAN and the over-driving pulse SAOVDP are activated, the transistors M1, M2 and M3 are respectively turned on to drive the RTO to a supply voltage VDD and the SB to a ground voltage VSS.
Thereafter, after passing a predetermined time period, the over-driving pulse SAOVDP is deactivated with a logic high level to drive the RTO to the core voltage VCORE. Then when a pre-charge command PCG is applied thereto, the pull-up and pull-down supply line driving control signals SAP and SAN are deactivated, and the RTO and the SB are precharged to a bit line pre-charge voltage VBLP by the BLSA supply line equalizing/pre-charging section 62. The bit line precharge voltage VBLP typically has a voltage level of a half of the core voltage VCORE, i.e., VCORE/2.
FIG. 5 is a simulation showing voltage and current changes according to the over-driving pulse SAOVDP under various power supply voltage conditions.
Under low power voltage condition where the power supply voltage VDD is about 1.6V and the core voltage VCORE is about 1.5V, there appear few problems in an over-driving operation of the over-driver. This is because a trend in a voltage lowering in a semiconductor memory device is considered at a design process and a size of the transistor M1 as an over-driver is also designed to apply a proper amount of current into the core voltage VCORE under the low voltage condition.
However, under high power voltage condition where the power supply voltage VDD is about 2V, the transistor M1 of the BLSA supply line driving unit 60 supplies an excessive current to the core voltage VCORE during an over-driving interval, such that the core voltage VCORE suddenly increases in its voltage level to thereby have an excessive voltage level. In case where a voltage level of the core voltage VCORE excessively rises as described above, there occurs a problem that an operational characteristic degrades to incur a poor device.
Meanwhile, as shown in FIG. 5, the over-driving pulse SAOVDP has a short active interval, i.e., a pulse width, under the high power voltage condition in comparison to that under low power voltage condition. This is because a propagation delay is decreased as the power voltage is increased. However, an effect thereof is insignificant.